The world’s most valuable supplier you never see on a box keeps pulling away. Taiwan Semiconductor Manufacturing Co. commands an extraordinary slice of outsourced chipmaking—and, crucially, the parts of the value chain that matter most for today’s AI-soaked designs. Industry trackers peg TSMC’s Q2 2025 foundry share around 70%, powered by insatiable orders from Nvidia, Apple and AMD. Scale is compounding into advantage: more leading-edge wafers, more packaging capacity, more customers hitching product road maps to TSMC’s calendar.

Lithography Economics Trump Node Names

The next two years will be defined less by who can announce a bleeding-edge node and more by who can print features cheaply and predictably. TSMC says its first gate-all-around nanosheet node, N2, is slated for volume production in late 2025, followed by the A16 platform—with backside power delivery—in 2026. That cadence gives customers performance headroom without forcing a premature bet on the costlier generation of extreme-ultraviolet tools. Meanwhile, the industry is still proving how to make High-NA EUV economical at scale, even as ASML and imec’s joint lab works to harden pellicles, resists and metrology. The message for chip buyers who live by performance-per-dollar-per-watt: waiting until the economics close is rational.

Intel is pushing 18A and signaling a follow-on 14A, but even Intel’s finance chief has acknowledged that 14A will cost more than 18A in part because it leans on those High-NA scanners. As High-NA pricing and uptime mature, that premium can shrink—but right now, higher wafer costs are a headwind to broad adoption. For a foundry challenger, selling “faster at higher cost” into a market optimized around TSMC’s price-performance curve is a tough pitch outside select HPC designs.

What’s going on at Intel (INTC)?

Intel is trying to rebuild the plane in mid-air. Since March, when longtime chip executive Lip-Bu Tan took the helm, the company has been in a rolling reset—reshuffling top jobs, rethinking how much to spend on its next manufacturing node, and striking an extraordinary pact with Washington that could

QMoat - Quality WinsQMoat

Inside the fabs, the operational battle is even more prosaic: EUV throughput, mask quality, inspection density and defect learning. The leaders squeeze more good die out of each scanner hour—and can afford to add inspection where it raises final yield. That kind of boring, expensive discipline widens gaps that press releases can’t close.

Packaging Becomes the Product

AI accelerators aren’t single slabs of silicon anymore; they’re clusters of chiplets, stitched to stacks of high-bandwidth memory across organic or silicon interposers. Getting that assembly right—at yield, at scale, with predictable thermals—is where TSMC’s CoWoS franchise has turned into a moat of its own. Industry reports indicate Nvidia has reserved the bulk of TSMC’s 2025 CoWoS-L capacity to feed its Blackwell ramp. The mix is shifting toward CoWoS-L to boost both performance and factory throughput, with output set to step higher again through 2026. When your packaging calendar is your customers’ product calendar, leverage piles up fast.

This packaging gravity also changes who really competes. The old separation—design houses on one side, foundries on the other—now blurs into “system foundry” models that promise tuned silicon, high-speed interconnects and memory co-planning. TSMC didn’t invent chiplets, but it industrialized them at scale, and its ecosystem around substrates, interposers and reliability modeling has become part of the selling proposition.

Challengers Must Thread a Narrow Needle

Could the center of gravity shift? Absolutely—over years, not quarters. Intel says first customer silicon on 18A is imminent, with volume set for 2026. If it lands marquee packaging wins on top of competitive 18A parts, the narrative can change quickly in data-center accelerators. But until 14A is both technically and economically proven, Intel will be selling into a market calibrated to TSMC’s yields, delivery and pricing—especially in mobile, where the ecosystem lock-in is strongest.

Samsung remains the other obvious challenger, particularly in phones where design wins convert swiftly to wafer starts. Yet the recent cycle has shown how unforgiving logic yields can be: momentum requires not just breakthroughs but months of stable, boring output. Capacity is nothing without consistency.

Here’s the kicker. Because rivals’ next big leap depends on costlier lithography and unproven learning curves, TSMC enjoys the luxury of advancing “just far enough”—pacing N2 and A16 while expanding packaging—and still defending its lead. In a business ruled by time, yield and capital intensity, that freedom to optimize economics rather than chase nanometers at any price is a moat all its own.

Bottom line

Over the next couple of years, expect TSMC to keep doing what compounding winners do—convert scale into better costs, convert better costs into stickier customers, and convert stickier customers into the next wave of scale. Challengers can and will take slices of specific markets. Dislodging the center will take longer—and a lot more than a shiny new node name.